The present invention relates to electrical circuitry, and more particularly to warpage reduction in structures with electrical circuitry. Exemplary structures include semiconductor integrated circuits.
FIG. 1 is a side view of a structure having one or more semiconductor integrated circuits (ICs) 110 bonded to a substrate 120 with solder 130. Substrate 120 can be another IC, or a packaging substrate such as an interposer, or a wiring board; substrate 120 may include conductive lines connecting the ICs 110 to each other or to other circuits. Additional features may be present, e.g. heat sink 160. ICs 110 and substrates 120 should preferably be planar as in FIG. 1, but they can be warped (FIGS. 2 and 3). Warpage causes vary. For example, in FIG. 4, IC 110 includes a semiconductor substrate 410 and an overlying layer 420 (e.g. metal) which was deposited at a high temperature and then cooled. In cooling, layer 420 shrank more than substrate 410 (because layer 420 has a higher coefficient of thermal expansion (CTE)), so the structure shrank on top more than the bottom (due to compressive stress on top). Warpage can also be as in FIG. 5 if substrate 410 shrinks more than layer 420 (tensile stress on top). Warpage may also be caused by shrinkage due to curing of a polymeric layer after deposition. In addition, warpage may relate to non-uniform heating and cooling rates; choice of materials; manufacturing parameters such as pressures, compositions, ambient, etc.; circuit design; and structural features, e.g. the particular placement of structural elements and their attachments and interconnections.
Warpage can damage the structure elements as illustrated in FIGS. 2 and 3. For example, in FIG. 2, the solder connections in the middle of IC 110 are farther from substrate 120 than at the edges. Consequently, the solder connections in the middle can crack or break, impeding electrical functionality. The same is true for the edge connections in FIG. 3. Of note, solder connections should preferably be small to reduce the lateral size of the structure, but the solder connections cannot be made small if they have to accommodate warpage. Warpage reduction is therefore highly desirable.
Warpage can be reduced by forming an extra layer in the IC to balance the warping stresses caused by other layers. For example, U.S. Pat. No. 7,169,685 issued Jan. 30, 2007 to Connell et al. describes a “stress balancing layer” formed on the wafer's backside to balance the stresses caused by a layer formed on the front side. Another example is U.S. Pre-Grant Publication no. 2010/0285654 A1 of U.S. patent application Ser. No. 12/839,573 by Seo, which describes forming a stress-relieving pattern in a layer formed over a substrate.